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1. Field of the Invention
The invention relates to a process for automatic generation of several electrical pulses using numeric default values, which process is particularly suitable for simulating an incremental encoder for sequential digital counting of pulses, where the counter result corresponds to linear or angular displacement values. A value generator is used which generates and outputs the default values repeatedly within allocated first cycle times. The default values are then used by cyclic detection, calculation and control means and a pulse switching interface controlled thereby which has one or more outputs for the pulses or pulse sequences. The invention further relates to a digital electronic data processing apparatus suitable for performance of the said process.
2. Description of the Related Art
Processes for generating parallel electrical pulse sequences are used in incremental methods of length and angle measurement (see e.g. Alfons Ernst xe2x80x9cDigital Length and Angle Measurement Technologyxe2x80x9d Verlag Moderne Industrie, Landsberg/Lech, page 8 ff). Sinusoidal sampling signals offset by 90xc2x0 to each other are converted by means of comparators into rectangular pulses giving two pulse sequences phase offset by 90xc2x0 to each other. These are supplied to a counter in which counting pulses are first derived from the signal flanks. At the same time the signals are passed to a direction discriminator which determines the counting direction and passes the counting pulses to the plus or minus input of an up and down counter. The counting result corresponds to the displacement path and can be shown in a display or supplied to a computer or controller. Such processes for determining the displacement path by counting pulses or measurement steps are known as incremental measurement processes.
Resolvers are also known which in conjunction with a suitable analysis circuit can implement an absolute measurement system within one revolution. By means of interpolation, measurement steps can be generated which are less than one-quarter of the period of the sampled signals. Known interpolators provide not only the interface for the absolute measurement system but optionally also an incremental interface to allow use in conjunction with conventional controls.
In particular in connection with the use of resolvers as position encoders it is known to simulate and output incremental encoder signals for subsequent control electronics (see DE journal xe2x80x9cElectronicsxe2x80x9d, Vol. 8/1994, page 48, page 60). Here the incremental encoder simulation is normally achieved using a position control circuit which outputs as a variable a set frequency for a frequency generator. Reference is made to the description below of FIG. 1 for further details. One disadvantage of this known solution is that this is a control circuit which can only work if a control deviation is present. Thus in the least favorable case, depending on the selected dynamics of the controller, even when stopped i.e. if an unchanging position is to be shown, a very high output frequency (up to more than 1 MHz by toggling of a track) can be present, which is difficult for following electronics to interpret. This time behavior of the control circuit can lead to an undesirable inherent dynamic of the entire adjustment and control system dependent on the incremental encoder simulation. A further disadvantage lies in the use of the frequency generator, the output pulses of which reflect only a nominal or set frequency but do not have a direct relation to the position default values for simulating the incremental encoder. Furthermore the necessary hardware expense cannot be ignored: as well as a position controller, a frequency generator and a counter module, summing points are also required (see FIG. 1 below). To remedy this, implementation of the control circuit in an existing signal processor is possible but this only allows limited sampling times in conjunction with a restricted frequency range, reduced resolution and non-optimum precision.
The invention is based on the object of specifying a process for incremental encoder simulation with increased resolution and precision, increased stability and operating reliability and a reduced complexity of the necessary hardware. The simulation should also be able to work with improved dynamics, where an improved linearity can be achieved in the correlation between the position change and the output pulse frequency. In addition the process primarily intended for incremental encoder simulation can be used outside this area of application as a general pulse-generating process for a multiplicity of further possible uses.
The object is achieved in a process with the features cited initially, in that the program and/or circuitry of the calculation and control means are designed:
to detect the current default value and determine the difference value from the current and a previous default value or an incremental value per first cycle time, which incremental value was counted up or down previously in accordance with previous default values or difference values,
to convert the difference value into control signals for the binary interface, a process which is repeated within several second cycle times, the total duration of which does not exceed the first cycle time of the value generator,
and to dimension the number or frequency of the pulses or pulse flanks triggered per first cycle time according to the difference value concerned, preferably directly proportional to the difference value.
The new solution approach is therefore characterized in that no control circuit is used as in the prior art; rather the pulses for example of tracks A and B in incremental encoder simulation are output controllably in direct proportional to the incoming position default value. This direct correlation of the pulse output to the incoming default, in particular position values, gives the advantage that when the default value remains unchanged, no further pulses or pulse flanks are output. Toggling of a track with very high frequency due to unavoidable inherent dynamics of control circuits is prevented with the solution according to the invention. The number or frequency of the output pulses or pulse flanks is dimensioned directly according to the difference value of two default values of different preferably successive cycle times of the value generator. If the default remains unchanged (which can e.g. correspond to a stopped position), the difference has the value of zero so the pulse switching interface is not switched to generate pulses.
According to an advantageous embodiment of the invention the default value is simulated internally in the calculation and control means via integration of the difference value from the previous default value or incremental value, where the integration calculation process is spread divided over the second cycle times occurring within a first cycle time. Depending on the result of the integration calculation process, in each of these second cycle times it is checked whether the pulse switching interface should be triggered to output corresponding pulses or pulse flanks.
According to a particularly advantageous process variant, within the calculation and control means a variable incremental value is kept or managed which tracks the current default value within each cycle time according to the difference value. During the tracking process, depending on the incrementing or decrementing, pulse or pulse flanks are generated via the pulse switching interface.
To produce an absolute correlation, in particular an absolute position, in incremental (measurement) counting processes it is normal to generate a so-called reference pulse. For this according to one embodiment of the invention it is provided that the calculation and control means contain one or more reference constants. Using these the incremental value can be compared continuously, preferably within every second cycle time. If however a separate reference pulse output is provided at the pulse switching interface, this output can be actuated on fulfillment of a comparison condition. One advantage achievable as a result is that the reference pulse can be generated both synchronously and asynchronously from the other pulse sequences, for example the incremental encoder tracks A and B.
A further advantage in the introduction and administration of the incremental value is that this can be increased and reduced divided over the second cycle times occurring in each first cycle time. Here the incremental value serves also as a guide value, on the change of which and/or depending on the amount of the difference value, the pulse switching interface is optionally triggered to output corresponding pulses or pulse flanks in each second cycle time, or in some cases not triggered to do so if in the latter case for example the amount of the difference value is less than the number of the second cycle times occurring per first cycle time.
When the pulse generation process according to the invention is used as an incremental encoder simulation, the incremental value can advantageously be interpreted as an output position measurement value of an imaginary incremental length or angle measurement system. Because of the rapid calculation and control means feasible with modern technology, in particular with very short possible second cycle times, the incremental or tracked default or position value has a resolution which can be very much greater than that of a real incremental measurement system. This achieves inter alia, the advantage that the said reference or xe2x80x9czeroxe2x80x9d pulse can be generated with far higher precision than for example in the incremental encoder simulation known from the prior art as mentioned above, in which the reference pulse is triggered depending on and synchronously with one flank of the pulse tracks.
In order to reduce the incremental value or corresponding position value to a resolution corresponding to a real incremental encoder, in an advantageous refinement the incremental or position measurement value is adapted by a reduction of the resolution to four times the line count of the imaginary incremental measurement system. The resolution with which the internal incremental value generated according to the invention is tracked arises from the reciprocal value of a second cycle time. The ratio between the first and second cycle times in the invention can lie between 50 and 50000, preferably between 500 and 10000, in particular if the value generator is achieved by means of sequential logic or software and the calculation and control means by fixed wired hardware, optionally after programming. Alternatively or in addition implementation with very rapid processors and software running sequentially thereon also lies within the scope of the invention.
The object cited above is achieved by a digital electronic data processing apparatus lying within the scope of the general inventive concept which is characterized as follows:
by one or more digital data registers working time-discretely, which can be loaded and read repeatedly at equidistant transmission times with the generated default values (for example from the value generator) and other parameters (for example ratio of first to second cycle times, incremental encoder line count, output value for reference pulse etc),
in which discrete working modes of the data register or registers correspond to the periods between the transition times of the above (longer) first cycle time,
by a sampling system working time-discretely with calculation and control systems designed to access the data register or registers within each first cycle time and process the register content within shorter time periods which correspond to the said second cycle time,
and by a pulse-generating logic to output pulse-like binary switching states.
The sampling system with the calculation and control system is thus intended for example to process the above incremental value with a considerably greater calculation speed than is the case in a value generator system with the time-discrete data register. To form the difference value essential for the process according to the invention, it is advantageous if the calculation and control system has a subtractor, a divider and a residual divider and/or one or another arithmetic unit which on the basis of the first cycle time obtains the default value from the data register and calculates the difference value using the default or incremental value tracked internally.
Suitably a coupling, in particular time-synchronous, between the value generator system with the data register and the sampling system for incremental encoder simulation can be implemented by an interrupt device which has priority over the calculation processes running in the calculation and control system on the basis of the second cycle time. Advantageously the logic pulse gate is controlled by a status variable administered in the calculation and control system and above all calculated at the end of each second cycle time, which variable is defined for a limited number of status values in preset sequence. The sequence can symbolize the movement or direction of rotation when used for incremental encoder simulation. Depending on the difference between the incremental values of a current second and a previous second cycle time, the status variable is kept constant or moved forwards or backwards by one step in the said value sequence. The pulse switching interface then allocates to the status variables the specific pulse pattern, for example two parallel phase-offset pulses at the gate output.
To achieve faster sampling times for the calculation and control system it is advantageous to program the process according to the invention in one or more complex programmable logic devices (CPLDs) and/or field-programmable gate arrays (FPGAs). For the pulse generation logic, simple and economic implementation possibilities are available by means of switching networks, for example in the form of programmable logic fields or fixed value memories (ROM). It is however particularly advantageous to integrate the pulse-generating logic constructionally with the calculation and control system as part of the above logic devices or gate arrays.
Further details, features, advantages and effects based on the invention arise from the description below of a preferred embodiment example of the invention in comparison with an example from the prior art, with reference to the drawings. These show: